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STM1 Framer

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STM1 Framer

STM1 Framer IP core provides a flexible and resource-efficient FPGA IP core. It can be configured as Framer or Deframer or both as required. STM1 Framer IP core can be imported into any user FPGA logic requiring STM1 framer/ deframer capability.

STM1 Framer Block Diagram

Features

Detects and aligns to the STM1 Framing Pattern
Synchronizes to the STM1 received frames and generates LOS, LOF and OOF alarms. Inserts framing bytes into the transmit STM1 frames.
Descrambles received STM1 Frames and Scrambles transmit STM1 frames. Scrambling / De-Scrambling can be enabled or disabled.
Integrates in built SERDES unit.
Extracts STM1 Payload for use in STM-1 / AU-3 or STM-1 / AU-4 interface applications, operating at serial interface speeds of 155.52 Mbit/s.
Provides termination for SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of three AU-3 paths or a single AU-4 path.
All the SDH transport and path overheads are extracted from the receive stream and are available for processing.
Interprets or generates the AU pointer bytes (H1, H2, H3), extracts or inserts the synchronous payload envelope(s), and processes or inserts the path overhead.
Detects B1, B2 and B3 parity errors.
Supports dual clock domains, facilitating the use of independent system and line clocks.
Provides microprocessor interface for configuration, control and status information processing.

Resource Utilization

The following figures are calculated assuming that all core IOs are routed off-chip. This results in a worst-case resource utilization figure, and for any given application the resource utilization is likely to be lower.

The core can be targeted for devices from other families and manufactures. Contact KritiKal Solutions Pvt. Ltd. for further details.

Stratx II Family
	Used By the Core
Combinational ALUTs	3482
Dedicated logic registers	1224
Total registers	1224
Total pins	244
Total block memory bits	36,864
Max. Freq	100 MHz

Virtex 2 Pro Family (E.g XCV2VP30)
	Used By Core	In Example Part	Percentage Used
Slice Registers	1383	3874	3%
Occupied Slices	2863	19392	14%
LUTs	5101	38784	13%
Block RAMs	2	192	1%
MULT18X18s	48	192	25%
IOBs	244	416	58%
Max. Freq.	100 Mhz

Applications

Interfacing with Digital / Optical Cross-Connects
ADM Aggregate Cards for TDM and Multi-service applications.
Terminal Multiplexers.
Interfacing with Tupp Plus, low order TU pointer processing.

STM1 Framer

Features

Resource Utilization

Applications

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