FPGA and CPLD Based Designs

We have experience of working with very intricate and complex FPGA designs based on VHDL and Verilog both. Our designs have successfully handled multiple clock domains and supported exceptionally high frequency of operations, as and when required. A typical FPGA development cycle is as follows:

 

FPGA Development Cycle

 

  • High speed board level design: We routinely handle high speed bus design issues with FPGAs and CPLDs, VHDL/Verilog, SoC, DSP functions etc. 
  • Expertise in single and multiple clock domain logic 
  • Expertise in hardware software co-design for FPGA based processors 
  • High speed communication based designs 
  • Expertise in advanced architectures 
    • Pipelined processor design 
    • Handling multi-million gate designs 
    • Interfacing with all kinds of digital devices / buses 
    • Implementing all kinds of custom DSP functions 
  • FPGA / CPLD design and verification
  • System on Chip (SoC) and ASIC development 
  • Customization and integration of intellectual properties 
  • Expertise in embedded processors like ARM, Power PC, Nios, MicroBlaze 
  • Thorough proficiency in implementation of protocols like Ethernet, TCP/IP/UDP/ARP/HTTP/FTP, HDLC, ATM
  • We adopt standard FPGA design and development methodologies: 
    • Assimilation - A thorough understanding of the client's design priorities 
    • Architectural review and optimization accompanied by a detailed project proposal 
    • FPGA design device selection and optimization 
    • Synchronous implementation and re-implementation, if required 
    • Critical timing analysis paired with functional simulation 
    • Implementation 
    • Final and actual design performance verification 
  • Design Expertise: 
    • Xilinx Spartan Series 
    • Xilinx VirtexII Series 
    • Xilinx Virtex4 Series 
    • Actel Pro-ASIC 

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